The NTE955MC is a monolithic timing circuit in an 8–Lead DIP type package fabricated using CMOS process. This timer is fully compatible with CMOS, TTL, and MOS logic and operates at frequencies up to 2MHz. Because of its high impedance, this device uses smaller timing capacitors than those used by the NE555. As a result, more accurate time delays and oscillations are possible. Power consumption is low across the full range of power supply voltage. Like the NE555, the NTE955MC has a trigger level equal to approximately one–third of the supply voltage and a threshold level equal to approximately two–thirds of the supply voltage. These levels can be altered by use of the control voltage terminal (Pin5). When the trigger input (Pin2) falls below the trigger level, the flip–flop is set and the output goes high. If Pin2 is above the trigger level and the threshold input (Pin6) is above the threshold level, the flip–flop is reset and the output is low. The reset input (Pin4) can override all other inputs and can be used to initiate a new timing cycle. If Pin4 is low, the flip–flop is reset and the output is low. Whenever the output is low, a low–impedance path is provided between the discharge terminal (Pin7) and GND. All unused inputs should be tied to an appropriate logic level to prevent false triggering. While the CMOS output is capable of sinking over 100mA and sourcing over 10mA, the NTE955MC exhibits greatly reduced supply–current spikes during output transitions. This minimizes the need for the large decoupling capacitors required by the NE555.
 
Full spec sheet:
https://www.nteinc.com/specs/900to999/pdf/nte955mc.pdf