NTE74LS109A Integrated Circuit TTL − Dual J−K Positive Edge Triggered Flip−Flop with Preset and Clear
Description: The NTE74LS109A contains two independent J−K positive−edge−triggered flip−flops in a 16−Lead plastic DIP type package. A low level at the preset or clear inputs sets or resets the outputs regardless of the levels of the other inputs. When preset and clear are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the positive−going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of th clock pulse. Following the hold time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. This versatile flip−flop can perform as a toggle flip−flop by grounding K and tying J high and also as a D−type flip−flop if J and K are tied together.
Full spec sheet: